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ai02078c 18 a0-a17 w dq0-dq7 v cc m29f002t m29f002b m29f002nt e v ss 8 g (*) rpnc figure 1. logic diagram m29f002t, m29f002nt m29f002b 2 mbit (256kb x8, boot block) single supply flash memory not for new design m29f002t, m29f002nt and m29f002b are replaced respectively by the m29f002bt, m29f002bnt and m29f002bb. 5v 10% supply voltage for program, erase and read operations fast access time: 70ns fast programming time: 10 m s typical program/erase controller (p/e.c.) C program byte-by-byte C status register bits memory blocks C boot block (top or bottom location) C parameter and main blocks block, multi-block and chip erase multi-block protection/temporary unprotection modes erase suspend and resume modes C read and program another block during erase suspend low power consumption C stand-by and automatic stand-by 100,000 program/erase cycles per block 20 years data retention C defectivity below 1ppm/year electronic signature C manufacturer code: 20h C device code, m29f002t: b0h C device code, m29f002nt: b0h C device code, m29f002b: 34h description the m29f002 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a byte-by-byte basis using only a single 5v v cc supply. for program and erase operations the necessary high voltages are generated internally. the device can also be pro- grammed in standard programmers. the array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. blocks can be protected against pro- graming and erase on programming equipment, and temporarily unprotected to make changes in july 2000 1/29 this is information on a product still in production but not recommended for new design. plcc32 (k) 32 1 pdip32 (p) tsop32 (n) 8 x 20mm note: * rpnc function is not available for the m29f002nt
ai02079c a17 a13 a10 dq5 17 a1 a0 dq0 dq1 dq2 dq3 dq4 a7 a4 a3 a2 a6 a5 9 w a8 1 a16 a9 dq7 a12 a14 32 rpnc v cc m29f002t m29f002b a15 a11 dq6 g e 25 v ss figure 2b. lcc pin connections a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a17 w a16 a12 (*) rpnc v cc a15 ai02080c m29f002t m29f002b m29f002nt 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 2a. dip pin connections a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 dq4 dq6 a17 w a16 a12 rpnc v cc a15 ai02361b m29f002t m29f002b 8 1 9 16 17 24 25 32 v ss figure 2c. tsop pin connections note: pin 1 is not connected for the m29f002nt a0-a17 address inputs dq0-dq7 data input/outputs, command inputs e chip enable g output enable w write enable rpnc (*) reset / block temporary unprotect v cc supply voltage v ss ground table 1. signal names description (contd) the application. each block can be programmed and erased over 100,000 cycles. instructions for read/reset, auto select for reading the electronic signature or block protection status, programming, block and chip erase, erase sus- pend and resume are written to the device in cycles of commands to a command interface using standard microprocessor write timings. the device is offered in plcc32, pdip32 and tsop32 (8 x 20 mm) packages. 2/29 m29f002t, m29f002nt, m29f002b
symbol parameter value unit t a ambient operating temperature (3) C40 to 125 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltages C0.6 to 7 v v cc supply voltage C0.6 to 7 v v (a9, e, g, rpnc) (2) a9, e, g, rpnc voltage C0.6 to 13.5 v notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliab ility. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns. 3. depends on range. table 2. absolute maximum ratings (1) organisation the m29f002 is organised as 256k x 8. memory control is provided by chip enable e, output enable g and write enable w inputs. a reset/block temporary unprotection rpnc (not available on m29f002nt) tri-level input pro- vides a hardware reset when pulled low, and when held high (at v id ) temporarily unprotects blocks previously protected allowing them to be progra- med and erased. erase and program operations are controlled by an internal program/erase con- troller (p/e.c.). status register data output on dq7 provides a data polling signal, and dq6 and dq2 provide toggle signals to indicate the state of the p/e.c operations. memory blocks the devices feature asymmetrically blocked archi- tecture providing system memory integration. the m29f002 has an array of 7 blocks, one boot block of 16 kbytes, two parameter blocks of 8 kbytes, one main block of 32 kbytes and three main blocks of 64 kbytes. the memory map is shown in figure 3. each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. the erase operations are managed automatically by the p/e.c. the block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed. block protection provides addi- tional data security. each block can be separately protected or unprotected against program or erase on programming equipment. all previously pro- tected blocks can be temporarily unprotected in the application. bus operations the following operations can be performed using the appropriate bus cycles: read (array, electronic signature, block protection status), write com- mand, output disable, standby, reset, block pro- tection, unprotection, protection verify, unprotection verify and block temporary unprotec- tion. see tables 4 and 5. command interface instructions, made up of commands written in cy- cles, can be given to the program/erase controller through a command interface (c.i.). for added data protection, program or erase execution starts after 4 or 6 cycles. the first, second, fourth and fifth cycles are used to input coded cycles to the c.i. this coded sequence is the same for all pro- gram/erase controller instructions. the command itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. any incor- rect command or any improper command se- quence will reset the device to read array mode. 3/29 m29f002t, m29f002nt, m29f002b
address range a17 a16 a15 a14 a13 00000h-0ffffh 0 0 x x x 10000h-1ffffh 0 1 x x x 20000h-2ffffh 1 0 x x x 30000h-37fffh 1 1 0 x x 38000h-39fffh 1 1 1 0 0 3a000h-3bfffh 1 1 1 0 1 3c000h-3ffffh 1 1 1 1 x table 3a. m29f002t, m29f002nt block address table address range a17 a16 a15 a14 a13 00000h-03fffh 0 0 0 0 x 04000h-05fffh 0 0 0 1 0 06000h-07fffh 0 0 0 1 1 08000h-0ffffh 0 0 1 x x 10000h-1ffffh 0 1 x x x 20000h-2ffffh 1 0 x x x 30000h-3ffffh 1 1 x x x table 3b. m29f002b block address table ai02081c 16k boot block 3ffffh 3c000h 3bfffh 3a000h 39fffh 00000h 8k parameter block 8k parameter block 32k main block 64k main block 64k main block 64k main block m29f002t, m29f002nt 38000h 37fffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 3ffffh 30000h 2ffffh 20000h 1ffffh 00000h 8k parameter block 8k parameter block 32k main block 64k main block 64k main block 64k main block m29f002b 10000h 0ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 16k boot block figure 3. memory map and block address table 4/29 m29f002t, m29f002nt, m29f002b
instructions seven instructions are defined to perform read array, auto select (to read the electronic signature or block protection status), program, block erase, chip erase, erase suspend and erase resume. the internal p/e.c. automatically handles all timing and verification of the program and erase opera- tions. the status register data polling, toggle, error bits may be read at any time, during program- ming or erase, to monitor the progress of the opera- tion. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interface which is common to all instruc- tions (see table 8). the third cycle inputs the in- struction set-up command. subsequent cycles output the addressed data, electronic signature or block protection status for read operations. in order to give additional data protection, the instruc- tions for program and block or chip erase require further command inputs. for a program instruction, the fourth command cycle inputs the address and data to be programmed. for an erase instruction (block or chip), the fourth and fifth cycles input a further coded sequence before the erase confirm command on the sixth cycle. erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. when power is first applied or if v cc falls below v lko , the command interface is reset to read array. signal descriptions see figure 1 and table 1. address inputs (a0-a17) . the address inputs for the memory array are latched during a write opera- tion on the falling edge of chip enable e or write enable w. when a9 is raised to v id , either a read electronic signature manufacturer or device code, block protection status or a write block protection or block unprotection is enabled depending on the combination of levels on a0, a1, a6, a12 and a15. data input/outputs (dq0-dq7). the input is data to be programmed in the memory array or a com- mand to be written to the c.i. both are latched on the rising edge of chip enable e or write enable w. the output is data from the memory array, the electronic signature manufacturer or device codes, the block protection status or the status register data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when chip enable e and output enable g are active. the output is high impedance when the chip is deselected or the outputs are disabled and when rpnc is at a low level. chip enable ( e). the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. e high deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memory array, while w remains at a low level. the chip enable must be forced to v id during the block unprotection opera- tion. output enable ( g). the output enable gates the outputs through the data buffers during a read operation. when g is high the outputs are high impedance. g must be forced to v id level during block protection and unprotection operations. write enable ( w). this input controls writing to the command register and address and data latches. reset/block temporary unprotect/no connect input ( rpnc). the rpnc (not available for the m29f002nt) input provides hardware reset and protected block(s) temporary unprotection func- tions. in read or write mode, the rpnc pin can be left open (not connected) or held at v ih . reset of the memory is acheived by pulling rpnc to v il for at least 500ns. when the reset pulse is given, if the memory is in read or standby modes, it will be available for new operations in 50ns after the rising edge of rpnc. if the memory is in erase, erase suspend or program modes the reset will take 10 m s. a hardware reset during an erase or program operation will corrupt the data being programmed or the sector(s) being erased. temporary block unprotection is made by holding rpnc at v id . in this condition previously protected blocks can be programmed or erased. the transi- tion of rpnc from v ih to v id must slower than 500ns. when rpnc is returned from v id to v ih all blocks temporarily unprotected will be again pro- tected. v cc supply voltage. the power supply for all op- erations (read, program and erase). v ss ground. v ss is the reference for all voltage measurements. device operations see tables 4, 5 and 6. read. read operations are used to output the con- tents of the memory array, the electronic signature, the status register or the block protection status. both chip enable e and output enable g must be low in order to read the output of the memory. 5/29 m29f002t, m29f002nt, m29f002b
operation e g w rpnc (6) a0 a1 a6 a9 a12 a15 dq0-dq7 read byte v il v il v ih v ih /nc (5) a0 a1 a6 a9 a12 a15 data output write byte v il v ih v il v ih /nc (5) a0 a1 a6 a9 a12 a15 data input output disable v il v ih v ih v ih /nc (5) x x x x x x hi-z standby v ih xxv ih /nc (5) x x x x x x hi-z reset (6) xx x v il x x x x x x hi-z block protection (2,4) v il v id v il pulse v ih /nc (5) xxxv id xx x blocks unprotection (4) v id v id v il pulse v ih /nc (5) xxxv id v ih v ih x block protection verify (2,4) v il v il v ih v ih /nc (5) v il v ih v il v id a12 a15 block protect status (3) block unprotection verify (2,4) v il v il v ih v ih /nc (5) v il v ih v ih v id a12 a15 block protect status (3) block temporary unprotection (6) xx x v id xxxxxx x notes: 1. x = v il or v ih 2. block address must be given on a13-a17 bits. 3. see table 6. 4. operation performed on programming equipment. 5. rpnc can be held at v ih or left open (not connected). 6. not available on m29f002nt. table 4. user bus operations (1) code device e g wa0a1 other addresses dq0 - dq7 manufact. code v il v il v ih v il v il dont care 20h device code m29f002t m29f002nt v il v il v ih v ih v il dont care b0h m29f002b v il vil v ih v ih v il dont care 34h table 5. read electronic signature (following as instruction or with a9 = v id ) code e g w a0 a1 a13 - a17 other addresses dq0 - dq7 protected block v il v il v ih v il v ih block address dont care 01h unprotected block v il v il v ih v il v ih block address dont care 00h table 6. read block protection with as instruction 6/29 m29f002t, m29f002nt, m29f002b
write. write operations are used to give instruction commands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w or e whichever occurs last. commands and input data are latched on the rising edge of w or e whichever occurs first. output disable. the data outputs are high imped- ance when the output enable g is high with write enable w high. standby. the memory is in standby when chip enable e is high and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs. automatic standby. after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the cmos standby value, while outputs still drive the bus. electronic signature. two codes identifying the manufacturer and the device can be read from the memory. these codes allow programming equip- ment or applications to automatically match their interface to the characteristics of the m29f002. the electronic signature is output by a read operation when the voltage applied to a9 is at v id and address input a1 is low. the manufacturer code is output when the address input a0 is low and the device code when this input is high. other address inputs are ignored. the electronic signature can also be read, without raising a9 to v id , by giving the memory the instruc- tion as. block protection. each block can be separately protected against program or erase on program- ming equipment. block protection provides addi- tional data security, as it disables all program or erase operations. this mode is activated when both a9 and g are raised to v id and an address in the block is applied on a13-a17. the block protection algorithm is shown in figure 14. block protection is initiated on the edge of w falling to v il . then after a delay of 100 m s, the edge of w rising to v ih ends the protection operations. block protection verify is achieved by bringing g, e, a0 and a6 to v il and a1 to v ih , while w is at v ih and a9 at v id . under these conditions, reading the data output will yield 01h if the block defined by the inputs on a13-a17 is protected. any attempt to program or erase a pro- tected block will be ignored by the device. block temporary unprotection. this feature is available on m29f002t and m29f002b only. any previously protected block can be temporarily un- protected in order to change stored data. the tem- porary unprotection mode is activated by bringing rpnc to v id . during the temporary unprotection mode the previously protected blocks are unpro- tected. a block can be selected and data can be modified by executing the erase or program in- struction with the rpnc signal held at v id . when rpnc is returned to v ih , all the previously pro- tected blocks are again protected. block unprotection. all protected blocks can be unprotected on programming equipment to allow updating of bit contents. all blocks must first be protected before the unprotection operation. block unprotection is activated when a9, g and e are at v id and a12, a15 at v ih . the block unprotection algorithm is shown in figure 15. unprotection is initiated by the edge of w falling to v il . after a delay of 10ms, the unprotection operation is ended by rising w to v ih . unprotection verify is achieved by bringing g and e to v il while a0 is at v il , a6 and a1 are at v ih and a9 remains at v id . in these conditions, reading the output data will yield 00h if the block defined by the inputs a13-a17 has been succesfully unprotected. each block must be sepa- rately verified by giving its address in order to ensure that it has been unprotected. instructions and commands the command interface latches commands written to the memory. instructions are made up from one or more commands to perform read memory array, read electronic signature, read block protection, program, block erase, chip erase, erase suspend and erase resume. commands are made of ad- dress and data sequences. hex code command 00h invalid/reserved 10h chip erase confirm 20h reserved 30h block erase resume/confirm 80h set-up erase 90h read electronic signature/ block protection status a0h program b0h erase suspend f0h read array/reset table 7. commands 7/29 m29f002t, m29f002nt, m29f002b
mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rd (2,4) read/reset memory array 1+ addr. (3,7) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,7) 555h aaah 555h read memory array until a new write cycle is initiated. data aah 55h f0h as (4) auto select 3+ addr. (3,7) 555h aaah 555h read electronic signature or block protection status until a new write cycle is initiated. see note 5 and 6. data aah 55h 90h pg program 4 addr. (3,7) 555h aaah 555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data be block erase 6 addr. (3,7) 555h aaah 555h 555h aaah block address additional block (8) data aah 55h 80h aah 55h 30h 30h ce chip erase 6 addr. (3,7) 555h aaah 555h 555h aaah 555h note 9 data aah 55h 80h aah 55h 10h es (10) erase suspend 1 addr. (3,7) x read until toggle stops, then read all the data needed from any block(s) not being erased then resume erase. data b0h er erase resume 1 addr. (3,7) x read data polling or toggle bits until erase completes or erase is suspended another time data 30h notes: 1. commands not interpreted in this table w ill default to r ead array mode. 2. a wait of t plyh is necessary after a read/reset command if the memory was in an erase or program mode before starting any new operation (see table 14 and figure 9). 3. x = dont care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the command cycles. 5. signature address bits a0, a1 at v il will output m anufacturer code (20h). address bits a0 at v ih and a1 at v il will output device code. 6. block protection address: a0 at v il , a1 at v ih and a13-a17 within the block will output the block protection status. 7. for coded cycles address inputs a12-a17 are dont care. 8. optional, additional blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through dq3 value (see erase timer bit dq3 description). when full command is entered, read data po lling or toggle bit until erase is completed or suspended. 9. read data po lling, toggle bits or r b until erase completes. 10.during erase suspend, read and data program functions are allowed in blocks not being erased. table 8. instructions (1) the instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruction. they are followed by either further write cycles to confirm the first com- mand or execute the command immediately. com- mand sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to assure maximum data security. instructions are initialised by two initial coded cycles which unlock the command inter- face. in addition, for erase, instruction confirmation is again preceded by the two coded cycles. status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 and erase timer dq3 bits. any read attempt during program or erase com- mand execution will automatically output these five status register bits. the p/e.c. automatically sets bits dq2, dq3, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked. see tables 9 and 10. 8/29 m29f002t, m29f002nt, m29f002b
dq name logic level definition note 7 data polling 1 erase complete or erase block in erase suspend indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. 0 erase on-going dq program complete or data of non erase block during erase suspend dq program on-going 6 toggle bit -1-0-1-0-1-0-1- erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete -1-1-1-1-1-1-1- erase complete or erase suspend on currently addressed block 5 error bit 1 program or erase error this bit is set to 1 in the case of programming or erase failure. 0 program or erase on-going 4 reserved 3 erase time bit 1 erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es). 0 erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c. 2 toggle bit -1-0-1-0-1-0-1- chip erase, erase or erase suspend on the currently addressed block. erase error due to the currently addressed block (when dq5 = 1). indicates the erase status and allows to identify the erased block 1 program on-going, erase on-going on another block or erase complete dq erase suspend read on non erase suspend block 1 reserved 0 reserved notes: logic level 1 is high, 0 is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. table 9. status register bits data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. during erase operation, it outputs a 0. after com- pletion of the operation, dq7 will output the bit last programmed or a 1 after erasing. data polling is valid and only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be performed at the address being programmed or at an address within the block being erased. if all the blocks se- lected for erasure are protected, dq7 will be set to 0 for about 100 m s, and then return to the previous addressed memory data value. 9/29 m29f002t, m29f002nt, m29f002b
see figure 11 for the data polling flowchart and figure 10 for the data polling waveforms. dq7 will also flag the erase suspend mode by switching from 0 to 1 at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an address within a block being erased must be provided. for a read operation in erase suspend mode, dq7 will output 1 if the read is attempted on a block being erased and the data value on other blocks. during program operation in erase sus- pend mode, dq7 will have the same behaviour as in the normal program execution outside of the suspend mode. toggle bit (dq6). when programming or erasing operations are in progress, successive attempts to read dq6 will output complementary data. dq6 will toggle following toggling of either g, or e when g is low. the operation is completed when two suc- cessive reads yield the same output data. the next read will output the bit last programmed or a 1 after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. if the blocks selected for erasure are pro- tected, dq6 will toggle for about 100 m s and then return back to read. dq6 will be set to 1 if a read operation is attempted on an erase suspend block. when erase is suspended dq6 will toggle during programming operations in a block different to the block in erase suspend. either e or g toggling will cause dq6 to toggle. see figure 12 for toggle bit flowchart and figure 13 for toggle bit waveforms. toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. it can also be used to identify the block being erased. during erase or erase suspend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will set dq2 to 1 during erase and to dq2 during erase suspend. during chip erase a read operation will cause dq2 to toggle as all blocks are being erased. dq2 will be set to 1 during program operation and when erase is complete. after erase completion and if the error bit dq5 is set to 1, dq2 will toggle if the faulty block is addressed. error bit (dq5). this bit is set to 1 by the p/e.c. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. in case of an error in block erase or program, the block in which the error occured or to which the programmed data belongs, must be dis- carded. the dq5 failure condition will also appear if a user tries to program a 1 to a location that is previously programmed to 0. other blocks may still be used. the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to 0 . erase timer bit (dq3). this bit is set to 0 by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the erase timeout period is finished, after 50 m s to 120 m s, dq3 returns to 1. coded cycles the two coded cycles unlock the command inter- face. they are followed by an input command or a confirmation command. the coded cycles consist of writing the data aah at address 555h during the first cycle. during the second cycle the coded cycles consist of writing the data 55h at address aaah. the address lines a0 to a11 are valid, other address lines are dont care. the coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. instructions see table 8. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read operations will read the memory array addressed and output the data read. a wait state of 10 m s is necessary after read/reset prior to any valid read if the memory was in an erase mode when the rd instruction is given. mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle note 1 erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle n/a note: 1. toggle if the address is within a block being erased. 1 if the address is within a block not being erased. table 10. polling and toggle bits 10/29 m29f002t, m29f002nt, m29f002b
ai01275b 3v high speed 0v 1.5v 2.4v standard 0.45v 2.0v 0.8v figure 4. ac testing input output waveform ai01276b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test figure 5. ac testing load circuit symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf note: 1. sampled only, not 100% tested. table 12. capacitance (1) (t a = 25 c, f = 1 mhz ) auto select (as) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 555h for command set-up. a subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of a0 and a1. the manufacturer code, 20h, is output when the addresses lines a0 and a1 are low, the device code is output when a0 is high with a1 low. the as instruction also allows access to the block protection status. after giving the as instruction, a0 is set to v il with a1 at v ih , while a13-a17 define the address of the block to be verified. a read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 555h on the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or e and the data to be written on the rising edge and starts the p/e.c. read operations output the status register bits after the programming has started. memory pro- gramming is made only by writing 0 in place of 1. status bits dq6 and dq7 determine if program- ming is on-going and dq5 allows verification of any possible error. programming at an address not in blocks being erased is also possible during erase suspend. in this case, dq2 will toggle at the ad- dress being programmed. high speed standard input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v table 11. ac measurement conditions 11/29 m29f002t, m29f002nt, m29f002b
symbol parameter test condition min max unit i li (2) input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i lr1 rpnc leakage current high rpnc = v cc 1 m a i lr2 rpnc leakage current low rpnc = v ss C0.2 C10 m a i cc1 supply current (read) ttl byte e = v il , g = v ih , f = 6mhz 20 ma i cc2 supply current (standby) ttl e = v ih 1ma i cc3 supply current (standby) cmos e = v cc 0.2v 100 m a i cc4 (1) supply current (program or erase) byte program, block or chip erase in progress 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage ttl i oh = C2.5ma 2.4 v output high voltage cmos i oh = C100 m a v cc C0.4v v v id a9, e, g, rpnc high voltage 11.5 12.5 v i id a9, e, g, rpnc high current a9, e, g or rpnc = v id 100 m a v lko supply voltage (erase and program lock-out) 3.2 4.2 v note: 1. sampled only, not 100% tested. 2. except rpnc. table 13. dc characteristics (t a = 0 to 70 c or C40 to 85 c; v cc = 5v 10%) block erase (be) instruction . this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address 555h on third cycle after the two coded cycles. the block erase confirm command 30h is similarly written on the sixth cycle after another two coded cycles. during the input of the second command an ad- dress within the block to be erased is given and latched into the memory. additional block erase confirm commands and block addresses can be written subsequently to erase other blocks in paral- lel, without further coded cycles. the erase will start after the erase timeout period (see erase timer bit dq3 description). thus, additional erase confirm commands for other blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the internal timer can be monitored through the level of dq3, if dq3 is 0 the block erase command has been given and the timeout is running, if dq3 is 1, the timeout has expired and the p/e.c. is erasing the block(s). if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the block with 00h as the p/e.c. will do this auto- matically before to erasing to ffh. read operations after the sixth rising edge of w or e output the status register status bits. during the execution of the erase by the p/e.c., the memory accepts only the erase suspend es and read/reset rd instructions. data polling bit dq7 returns 0 while the erasure is in progress and 1 when it has completed. the toggle bit dq2 and dq6 toggle during the erase operation. they stop when erase is completed. after completion the status register bit dq5 returns 1 if there has been an erase failure. in such a situation, the toggle bit dq2 can be used to determine which block is not correctly erased. in the case of erase failure, a read/reset rd instruction is necessary in order to reset the p/e.c. 12/29 m29f002t, m29f002nt, m29f002b
symbol alt parameter test condition m29f002t / m29f002nt / m29f002b unit -70 -90 -120 v cc = 5v 10% v cc = 5v 10% v cc = 5v 10% standard interface standard interface standard interface min max min max min max t avav t rc address valid to next address valid e = v il , g = v il 70 90 120 ns t avqv t acc address valid to output valid e = v il , g = v il 70 90 120 ns t elqx (1) t lz chip enable low to output transition g = v il 000ns t elqv (2) t ce chip enable low to output valid g = v il 70 90 120 ns t glqx (1) t olz output enable low to output transition e = v il 000ns t glqv (2) t oe output enable low to output valid e = v il 30 35 50 ns t ehqx t oh chip enable high to output transition g = v il 000ns t ehqz (1) t hz chip enable high to output hi-z g = v il 20 20 30 ns t ghqx t oh output enable high to output transition e = v il 000ns t ghqz (1) t df output enable high to output hi-z e = v il 20 20 30 ns t axqx t oh address transition to output transition e = v il , g = v il 000ns t plel (1,3) t ready rpnc low to read mode 10 10 10 m s t phel t rsp rpnc high to chip enable low 50 50 50 ns t plpx t rp rpnc pulse width 500 500 500 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . 3. to be considered only if the reset pulse is given while the memory is in erase mode. table 14. read ac characteristics (t a = 0 to 70 c or C40 to 85 c) 13/29 m29f002t, m29f002nt, m29f002b
ai02082 tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a17 e g dq0-dq7 telqv valid address valid and chip enable output enable data valid tehqz tghqz figure 6. read mode ac waveforms note: write enable ( w) = high 14/29 m29f002t, m29f002nt, m29f002b
symbol alt parameter m29f002t / m29f002nt / m29f002b unit -70 -90 -120 v cc = 5v 10% v cc = 5v 10% v cc = 5v 10% standard interface standard interface standard interface min max min max min max t avav t wc address valid to next address valid 70 90 120 ns t elwl t cs chip enable low to write enable low 000ns t wlwh t wp write enable low to write enable high 35 45 50 ns t dvwh t ds input valid to write enable high 30 45 50 ns t whdx t dh write enable high to input transition 000ns t wheh t ch write enable high to chip enable high 000ns t whwl t wph write enable high to write enable low 20 20 20 ns t avwl t as address valid to write enable low 5 5 5 ns t wlax t ah write enable low to address transition 45 45 50 ns t ghwl output enable high to write enable low 000ns t vchel t vcs v cc high to chip enable low 50 50 50 m s t whgl t oeh write enable high to output enable low 000ns t phphh (1,2) t vidr rpnc rise time to v id 500 500 500 ns t plpx t rp rpnc pulse width 500 500 500 ns notes: 1. sample only, not 100% tested. 2. this timing is for temporary block unprotection operation. table 15. write ac characteristics, write enable controlled (t a = 0 to 70 c or C40 to 85 c) chip erase (ce) instruction. this instruction uses six write cycles. the erase set-up command 80h is written to address 555h on the third cycle after the two coded cycles. the chip erase confirm command 10h is similarly written on the sixth cycle after another two coded cycles. if the second com- mand given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing it to ffh. read operations after the sixth rising edge of w or e output the status register bits. during the execu- tion of the erase by the p/e.c., data polling bit dq7 returns 0, then 1 on completion. the toggle bits dq2 and dq6 toggle during erase operation and stop when erase is completed. after completion the status register bit dq5 returns 1 if there has been an erase failure. 15/29 m29f002t, m29f002nt, m29f002b
ai02083 e g w a0-a17 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl figure 7. write ac waveforms, w controlled note: address are latched on the falling edge of w, data is latched on the rising edge of w. erase suspend (es) instruction. the block erase operation may be suspended by this instruction which consists of writing the command b0h without any specific address. no coded cycles are re- quired. it permits reading of data from another block and programming in another block while an erase operation is in progress. erase suspend is accepted only during the block erase instruction execution. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit dq6 stops toggling when the p/e.c. is suspended. the toggle bits will stop toggling between 0.1 m s and 15 m s after the erase suspend (es) command has been written. the device will then automatically be set to read mem- ory array mode. when erase is suspended, a read from blocks being erased will output dq2 toggling and dq6 at 1. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instructions. a program op- eration can be initiated during erase suspend in one of the blocks not being erased. it will result in both dq2 and dq6 toggling when the data is being programmed. a read/reset command will defini- tively abort erasure and result in invalid data in the blocks being erased. erase resume (er) instruction. if an erase sus- pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. power supply power up the memory command interface is reset on power up to read array. either e or w must be tied to v ih during power up to allow maximum security and the possibility to write a command on the first rising edge of e and w. any write cycle initiation is blocked when vcc is below v lko . supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v cc rail decoupled with a 0.1 m f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v cc program and erase currents required. 16/29 m29f002t, m29f002nt, m29f002b
symbol alt parameter m29f002t / m29f002nt / m29f002b unit -70 -90 -120 v cc = 5v 10% v cc = 5v 10% v cc = 5v 10% standard interface standard interface standard interface min max min max min max t avav t wc address valid to next address valid 70 90 120 ns t wlel t ws write enable low to chip enable low 000ns t eleh t cp chip enable low to chip enable high 35 45 50 ns t dveh t ds input valid to chip enable high 30 45 50 ns t ehdx t dh chip enable high to input transition 555ns t ehwh t wh chip enable high to write enable high 000ns t ehel t cph chip enable high to chip enable low 20 20 20 ns t avel t as address valid to chip enable low 000ns t elax t ah chip enable low to address transition 45 45 50 ns t ghel output enable high chip enable low 000ns t vchwl t vcs v cc high to write enable low 50 50 50 m s t ehgl t oeh chip enable high to output enable low 000ns t phphh (1,2) t vidr rpnc rise time to v id 500 500 500 ns t plpx t rp rpnc pulse width 500 500 500 ns notes: 1. sample only, not 100% tested. 2. this timing is for temporary block unprotection operation. table 16. write ac characteristics, chip enable controlled (t a = 0 to 70 c or C40 to 85 c) 17/29 m29f002t, m29f002nt, m29f002b
ai02084 e g w a0-a17 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel figure 8. write ac waveforms, e controlled note: address are latched on the fa lling edge of e, data is latched on the rising edge of e. ai02085 e rpnc tplpx tphel tplel tphphh figure 9. read and write ac characteristics, rp related 18/29 m29f002t, m29f002nt, m29f002b
symbol alt parameter m29f002t / m29f002nt / m29f002b unit -70 -90 -120 v cc = 5v 10% v cc = 5v 10% v cc = 5v 10% standard interface standard interface standard interface min max min max min max t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 10 2400 10 2400 m s write enable high to dq7 valid (chip erase, w controlled) 1.0 30 1.0 30 1.0 30 sec t ehq7v chip enable high to dq7 valid (program, e controlled) 10 2400 10 2400 10 2400 m s chip enable high to dq7 valid (chip erase, e controlled) 1.0 30 1.0 30 1.0 30 sec t q7vqv q7 valid to output valid (data polling) 30 35 50 ns t whqv write enable high to output valid (program) 10 2400 10 2400 10 2400 m s write enable high to output valid (chip erase) 1.0 30 1.0 30 1.0 30 sec t ehqv chip enable high to output valid (program) 10 2400 10 2400 10 2400 m s chip enable high to output valid (chip erase) 1.0 30 1.0 30 1.0 30 sec note: 1. all other timings are defined in read ac characteristics table. table 17. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c or C40 to 85 c) 19/29 m29f002t, m29f002nt, m29f002b
ai02086 e g w a0-a17 dq7 ignore valid dq0-dq6 address (within blocks) data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv figure 10. data polling dq7 ac waveforms 20/29 m29f002t, m29f002nt, m29f002b
read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 11. data polling flowchart read dq2, dq5 & dq6 start read dq2, dq6 fail pass ai01873 dq2, dq6 = toggle no no yes yes dq5 = 1 no yes dq2, dq6 = toggle figure 12. data toggle flowchart parameter m29f002t / m29f002nt / m29f002b unit min typ typical after 100k w/e cycles chip erase (preprogrammed) 0.7 0.9 sec chip erase 2.4 2.5 sec boot block erase 0.6 sec parameter block erase 0.5 sec main block (32kb) erase 0.9 sec main block (64kb) erase 1.0 sec chip program (byte) 3.2 3.2 sec byte program 11 11 m s program/erase cycles (per block) 100,000 cycles table 18. program, erase times and program, erase endurance cycles (t a = 0 to 70 c) 21/29 m29f002t, m29f002nt, m29f002b
ai02087 e g w a0-a17 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5,dq7 figure 13. data toggle dq6, dq2 ac waveforms note: all other timings are as a normal read cycle. 22/29 m29f002t, m29f002nt, m29f002b
block address on a13-a17 ai02088b g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih verify block protection a0, a6 = v il ; a1 = v ih ; a9 = v id a13-a17 identify block a9 = v ih ++n = 25 start fail pass yes no data = 01h yes no a9 = v ih set-up protect verify w = v ih wait 4s wait 60ns g = v il verify block protect status e = v il figure 14. block protection flowchart 23/29 m29f002t, m29f002nt, m29f002b
protect all blocks ai02089c data e, g, a9 = v id a12, a15 = v ih wait 4s w = v ih e, g = v ih wait 10ms = 00h next block w = v il ++n = 1000 start a9 = v ih yes yes no a9 = v ih no last blk. yes no n = 0 set-up unprotect verify w = v ih e, a0 = v il ; a1, a6 = v ih ; a9 = v id a13-a17 identify block wait 4s wait 60ns g = v il verify block protect status fail pass figure 15. all blocks unprotecting flowchart 24/29 m29f002t, m29f002nt, m29f002b
ordering information scheme m29f002t, m29f002nt and m29f002b are replaced respectively by the new version m29f002bt, m29f002bnt and m29f002bb. devices are shipped from the factory with the memory content erased (to ffh). for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. operating voltage f5v array matrix t top boot b bottom boot nt top boot without rpnc function speed -70 70ns -90 90ns -120 120ns power supplies blank v cc 10% x v cc 5% package p pdip32 k plcc32 n tsop32 (8 x 20 mm) option tr tape & reel packing temp. range 1 0 to 70 c 6 C40 to 85 c example: m29f002t -70 x k 1 tr 25/29 m29f002t, m29f002nt, m29f002b
pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2 symb mm inches typ min max typ min max a C 5.08 C 0.200 a1 0.38 C 0.015 C a2 3.56 4.06 0.140 0.160 b 0.38 0.51 0.015 0.020 b1 1.52 C C 0.060 C C c 0.20 0.30 0.008 0.012 d 41.78 42.04 1.645 1.655 d2 38.10 C C 1.500 C C e 15.24 C C 0.600 C C e1 13.59 13.84 0.535 0.545 e1 2.54 C C 0.100 C C ea 15.24 C C 0.600 C C eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 1.78 2.03 0.070 0.080 a 0 10 0 10 n32 32 drawing is not to scale. pdip32 - 32 pin plastic dip, 600 mils width 26/29 m29f002t, m29f002nt, m29f002b
plcc d ne e1 e 1 n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 symb mm inches typ min max typ min max a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 C 0.38 C 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 C C 0.050 C C f 0.00 0.25 0.000 0.010 r 0.89 C C 0.035 C C n32 32 nd 7 7 ne 9 9 cp 0.10 0.004 drawing is not to scale. plcc32 - 32 lead plastic leaded chip carrier, rectangular 27/29 m29f002t, m29f002nt, m29f002b
tsop32 - 32 lead plastic thin small outline, 8 x 20mm tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.007 a2 0.95 1.05 0.037 0.041 b 0.15 0.27 0.006 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.90 8.10 0.311 0.319 e 0.50 - - 0.020 - - l 0.50 0.70 0.020 0.028 a 0 5 0 5 n32 32 cp 0.10 0.004 drawing is not to scale. 28/29 m29f002t, m29f002nt, m29f002b
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ? 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 29/29 m29f002t, m29f002nt, m29f002b

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